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Tested 8bits desktop memory ram ddr3 4gbTested 8bits desktop memory ram ddr3 4gbTested 8bits desktop memory ram ddr3 4gbTested 8bits desktop memory ram ddr3 4gb

Tested 8bits desktop memory ram ddr3 4gb

  • Products Status: Stock
  • Application: Desktop
  • Memory Capacity: 4GB
  • Type: DDR3
  • Function: ECC
  • Frequency : 1066,1333,1600mhz
  • Brand Name: OEM memory ddr3 4gb 1333
  • Model Number: ETT original chips 8bits desktop memory ram ddr3 4gb
  • Place of Origin: Guangdong, China (Mainland)
  • Certificate: CE RoHS FCC
  • Brand supply: OEM ODM clients logo
  • RMA: Less than 1% memory ddr3 4gb 1333
  • Feature: Work with all motherboard
  • Chipsets: Original chipsets memory ddr3 4gb 1333
  • Packing: Bulk packing or retail packing
  • Delivery time: 2-3 working days memory ddr3 4gb 1333
  • Warranty: lifetime memory ddr3 4gb 1333
  • Factory website: www.ramjoinwin.com
  • Service: Support clients tested before pay

ETT original chips 8bits desktop memory ram ddr3 4gb

Memory Type: DDR3

Memory Speed: 1066/1333/1600MHz DDR3

Memory Size: 1GB/2B/4GB/8GB

Memory Channels: Dual

Memory Socket: LONG DIMM

Memory CAS Latency: 4-4-4-12

Memory Timing:4-4-4-12

Pins:240pin

Voltage:1.5V

Function: Non ECC Memory

Chip: Original chips ( brand new )

Warranty:Life time

 

Detail Description:

1) DDR 400/333 & DDRII 533/667/800 & DDR3/1066/1333/1600 MHz.
2) 168/184/240-pin socket type dual in line memory module (DIMM) .
3) 2.6V power supply
4) Data rate: 400/333/533/667/800M1066/1333MHZ/1600mhz (max). 
5) 2.5 V (SSTL-2 compatible) I/O for DDR I products, 1.8Vpower supply for DDR II products 
6) Double-data-rate architecture, two data transfers per clock cycle. 
7) Bi-directional, differential data strobe (DQS) is transmitted/received with data, to be

 used in capturing data at the receiver
8) Data inputs and outputs are synchronzed with DQS.
9) DQS is edge aligned with data for read, center aligned with data for write.
10) Differential clock inputs (CK and CK).
11) DLL aligns DQ and DQS transitions with CK transitions
12) Commands entered on each positive CK edge: Data and data mask referenced to both edges of DQS.
13) Four internal banks for concurrent operation (component). 
14) Data mask(DM) for write data. 
15) Auto precharge option for each burst access
16) Programmable burst length: 2, 4, 8 
17) Programmable/CAS latency (CL): 3 
18) Programmable output driver strength: Normal/weak 
19) Refresh cycles: (8192 refresh cycles/64ms) .
20) 7.8US maximum average periodic refresh interval.
21) Posted CAS by programmable additive latency for better command and data bus efficiency 
22) Off-chip-driver impedance adjustment and on-die-termination for better signal quality .
23) DQS can be disabled for single-ended data strobe operation 
24) 2 variations of refresh
25) Auto refresh 
26) Self refresh.